Weibull Distribution is one of most important distribution and it is mainly used in reliability and in distribution of life time. The study handled two parameter and three-parameter Weibull Distribution in addition to five –parameter Bi-Weibull distribution. The latter being very new and was not mentioned before in many of the previous references. This distribution depends on both the two parameter and the three –parameter Weibull distributions by using the scale parameter (α) and the shape parameter (b) in the first and adding the location parameter (g)to the second and then joining them together to produce a distribution with five parameters.

المتغير العشوائي X  له توزيع أسي اذا كان له دالة احتمالية الكثافة بالشكل:

عندما  ، هذه هي الحالة الخاصة لتوزيع كاما.

غالباً جداً ولسبب معقول تأخذ . الحالة الخاصة لـ (1) التي نحصل عليها تسمى بالتوزيع الاسي لمعلمة واحدة.

اذا كانت  ، ، التوزيع في هذه الحالة يسمى التوزيع الاسي القياسي

اما بالنسب

   A comparison of double informative and non- informative priors assumed for the parameter of Rayleigh distribution is considered. Three different sets of double priors are included, for a single unknown parameter of Rayleigh distribution. We have assumed three double priors: the square root inverted gamma (SRIG) - the natural conjugate family of priors distribution, the square root inverted gamma – the non-informative distribution, and the natural conjugate family of priors - the non-informative distribution as double priors .The data is generating form three cases from Rayleigh distribution for different samples sizes (small, medium, and large). And Bayes estimators for the parameter is derived under a squared erro

The use of Bayesian approach has the promise of features indicative of regression analysis model classification tree to take advantage of the above information by, and ensemble trees for explanatory variables are all together and at every stage on the other. In addition to obtaining the subsequent information at each node in the construction of these classification tree. Although bayesian estimates is generally accurate, but it seems that the logistic model is still a good competitor in the field of binary responses through its flexibility and mathematical representation. So is the use of three research methods data processing is carried out, namely: logistic model, and model classification regression tree, and bayesian regression tree mode

Error control schemes became a necessity in network-on-chip (NoC) to improve reliability as the on-chip interconnect errors increase with the continuous shrinking of geometry. Accordingly, many researchers are trying to present multi-bit error correction coding schemes that perform a high error correction capability with the simplest design possible to minimize area and power consumption. A recent work, Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB), showed a huge reduction in area and power consumption compared to a well-known scheme, namely, Hamming product code (HPC) with Type-II HARQ. Moreover, the authors showed that the proposed scheme can correct 11 random errors which is considered a high

Incremental forming is a flexible sheet metal forming process which is performed by utilizing simple tools to locally deform a sheet of metal along a predefined tool path without using of dies. This work presents the single point incremental forming process for producing pyramid geometry and studies the effect of tool geometry, tool diameter, and spindle speed on the residual stresses. The residual stresses were measured by ORIONRKS 6000 test measuring instrument. This instrument was used with four angles of (0º,15º,30º, and 45º) and the average value of residual stresses was determined, the value of the residual stress in the original blanks was (10.626 MPa). The X-ray diffraction technology was used to measure the residual stresses

Ensuring reliable data transmission in Network on Chip (NoC) is one of the most challenging tasks, especially in noisy environments. As crosstalk, interference, and radiation were increased with manufacturers' increasing tendency to reduce the area, increase the frequencies, and reduce the voltages.  So many Error Control Codes (ECC) were proposed with different error detection and correction capacities and various degrees of complexity. Code with Crosstalk Avoidance and Error Correction (CCAEC) for network-on-chip interconnects uses simple parity check bits as the main technique to get high error correction capacity. Per this work, this coding scheme corrects up to 12 random errors, representing a high correction capac