Sub-threshold operation has received a lot of attention in limited performance applications.However, energy optimization of sub-threshold circuits should be performed with the concern of the performance limitation of such circuit. In this paper, a dual size design is proposed for energy minimization of sub-threshold CMOS circuits. The optimal downsizing factor is determined and assigned for some gates on the off-critical paths to minimize the energy at the maximum allowable performance. This assignment is performed using the proposed slack based genetic algorithm which is a heuristic-mixed evolutionary algorithm. Some gates are heuristically assigned to the original and the downsized design based on their slack time determined by static timing analysis. Other gates are subjected to the genetic algorithm to perform an optimal downsizing assignment taking into account the previous assignments. The algorithm is applied for different downsizing factors to determine the optimal dual size for low energy operation without a performance degradation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74283, 74L85, ALU74181, and 16 bit ripple carry adder. The proposed design shows an energy per cycle saving ranged from (29.6% to 56.59%) depending on the utilization of available slack time from the off-critical paths. © School of Engineering, Taylor’s University.
The research (Virtual Reality Technology and its Uses in Industrial Product Design) is interested in the virtual reality technology used in the industrial product design and consequently knowing the functions achieved in the industrial product according to the data of that technology which participates in activating the mental and imaginary image of the user which show the parameters of the technical transformation of that product. The terms used in the research have been defined to guide the reader. The second chapter, the theoretical framework consisted of three sections the first is concerned with technology in the industrial design. The second is concerned with the virtual environment and the virtual reality. The thirds chapter consi
... Show MoreIt is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.
Developing and researching antenna designs are analogous to excavating in an undiscovered mine. This paper proposes a multi-band antenna with a new hexagonal ring shape, theoretically designed, developed, and analyzed using a CST before being manufactured. The antenna has undergone six changes to provide the best performance. The results of the surface current distribution and the electric field distribution on the surface of the hexagonal patch were theoretically analyzed and studied. The sequential approach taken to determine the most effective design is logical, and prevents deviation from the work direction. After comparing the six theoretical results, the fifth model proved to be the best for making a prototype. Measured results rep
... Show MoreThe problem in the design of a cam is the analyzing of the mechanisms and dynamic forces that effect on the family of parametric polynomials for describing the motion curve. In present method, two ways have been taken for optimization of the cam size, first the high dynamic loading (such that impact and elastic stress waves propagation) from marine machine tool which translate by the roller follower to the cam surface and varies with time causes large contact loads and second it must include the factors of kinematics features including the acceleration, velocity, boundary condition and the unsymmetrical curvature of the cam profile for the motion curve.
In the theoretical solution
... Show MoreThis paper proposes an on-line adaptive digital Proportional Integral Derivative (PID) control algorithm based on Field Programmable Gate Array (FPGA) for Proton Exchange Membrane Fuel Cell (PEMFC) Model. This research aims to design and implement Neural Network like a digital PID using FPGA in order to generate the best value of the hydrogen partial pressure action (PH2) to control the stack terminal output voltage of the (PEMFC) model during a variable load current applied. The on-line Particle Swarm Optimization (PSO) algorithm is used for finding and tuning the optimal value of the digital PID-NN controller (kp, ki, and kd) parameters that improve the dynamic behavior of the closed-loop digital control fue
... Show MoreAuthors in this work design efficient neural networks, which are based on the modified Levenberg - Marquardt (LM) training algorithms to solve non-linear fourth - order three -dimensional partial differential equations in the two kinds in the periodic and in the non-periodic - Periodic. Software reliability growth models are essential tools for monitoring and evaluating the evolution of software reliability. Software defect detection events that occur during testing and operation are often treated as counting processes in many current models. However, when working with large software systems, the error detection process should be viewed as a random process with a continuous state space, since the number of faults found during testin
... Show MoreInternational companies are striving to reduce their costs and increase their profits, and these trends have produced many methods and techniques to achieve these goals. these methods is heuristic and the other Optimization.. The research includes an attempt to adapt some of these techniques in the Iraqi companies, and these techniques are to determine the optimal lot size using the algorithms Wagner-Whitin under the theory of constraints. The research adopted the case study methodology to objectively identify the problem of research, namely determining lot size optimal for each of the products of electronic measurement laboratory in Diyala and in light of the bottlenecks in w
... Show MoreBackground: Poly-ether-ether-ketone(PEEK) has been introduced to many dental fields. Recently it was tested as a retainer wire‎ following orthodontic treatment. This study aimed to investigate the effect of changing the bonding spot size and location on the performance of PEEK retainer wires. Methods: A biomechanical study involving four three-dimensional finite element models was performed. The basic model was with a 0.8 mm cylindrical cross-section PEEK wire, bonded at the center of the lingual surface of the mandibular incisors with 4 mm in diameter composite spots. Two other models were designed with 3 mm and 5 mm composite sizes. The last model was created with the composite bonding spot of the canine away from the center of t
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