Channel estimation (CE) is essential for wireless links but becomes progressively onerous as Fifth Generation (5G) Multi-Input Multi-Output (MIMO) systems and extensive fading expand the search space and increase latency. This study redefines CE support as the process of learning to deduce channel type and signal-tonoise ratio (SNR) directly from per-tone Orthogonal Frequency-Division Multiplexing (OFDM) observations,with blind channel state information (CSI). We trained a dual deep model that combined Convolutional Neural Networks (CNNs) with Bidirectional Recurrent Neural Networks (BRNNs). We used a lookup table (LUT) label for channel type (class indices instead of per-tap values) and ordinal supervision for SNR (0–20 dB,5-dB steps). T
... Show MoreThis study was conducted in Diyala province for renal failure patients during the periods August 2015 - April 2016. Hundred renal failure patients were enrolled in the study after diagnosis by the consultant physician at Ibn-Sina Center for Dialysis in Baquba Teaching Hospital according to criteria adopted by the World Health Organization for diagnosis of renal failure disease. The number of males in patient’s sample was 61 (61%) and females was 39 (39%) with an age range of 10 – 88 year (44.7 ± 22.1 year). In addition, the study included 50 apparently healthy individuals and considered as a group control, in which the number of males and females was similar (25 individual), with an age range of 18 – 88 year (51.7 ± 17.3 year). The
... Show MoreThis study presents the debonding propagation in single NiTi wire shape memory alloy into linear low-density polyethylene matrix composite the study of using the pull-out test. The aim of this study is to investigate the pull-out tests to check the interfacial strength of the polymer composite in two cases, with activation NiTinol wire and without activation. In this study, shape memory alloy NiTinol wire 2 mm diameter and linear fully annealed straight shape were used. The study involved experimental and finite element analysis and eventually comparison between them. This pull-out test is considered a substantial test because its results have a relation with behavior of smart composite materials. The pull-out test was carried out by a u
... Show MoreHerein, we report designing a new Δ (delta‐shaped) proton sponge base of 4,12‐dihydrogen‐4,8,12‐triazatriangulene (compound
Q-switch Nd: YAG laser of wavelengths 235nm and 1,460nm with energy in the range 0.2 J to 1J and 1Hz repetition rate was employed to synthesis Ag/Au (core/shell) nanoparticles (NPs) using pulse laser ablation in water. In this synthesis, initially the silver nano-colloid prepared via ablation target, this ablation related to Au target at various energies to creat Ag/Au NPs. Surface Plasmon Resonance (SPR), surface morphology and average particle size identified employing: UV-visible spectrophotometer, scanning electron microscopy (SEM) and transmission electron microscopy (TEM). The absorbance spectra of Ag NPs and Ag/Au NPs showed sharp and single peaks around 400nm and 410nm, respec
A hybrid Gas-Enhanced and Downhole Water Sink-Assisted Gravity Drainage (GDWS-AGD) process has been suggested to enhance oil recovery by placing vertical injectors for CO2 at the top of the reservoir with a series of horizontal oil-producing and water-drainage wells located above and below the oil-water contact, respectively. The injected gas builds a gas cap that drives the oil to the (upper) oil-producing wells while the bottom water-drainage wells control water cresting. The hybrid process of GDWS-AGD process has been first developed and tested in vertical wells to minimize water cut in reservoirs with bottom water drive and strong water coning tendencies. The wells were dual-compl
It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.