The study involved the synthesis of new complexes with tetradentate ligand (LH). The general formula of complexes was [M(LH)(H2O)2] with M of Ni2+, Co2+, Cu2+, and Zn+. The ligand was synthesized by treating the 2-hydroxybenzohydrazide with salicylaldehyde. The structural characteristics of ligands and complexes were analyzed using various techniques, including elemental analyses, magnetic susceptibility, molar conductivity, infrared, ultraviolet absorption, mass, and NMR spectroscopy studies. The physical measurements indicated that the prepared complexes are non-electrolyte and showed that the ligand is tetradentate when coordinated with metal ions through the nitrogen of azomethine (–C=N–), two oxygen atoms of O–H phenolic,

Synthesis of a new class of Schiff-base ligand with a tetrazole moiety to form polymeric metal complexes with Co^II, Ni^II, Zn^II, and Cd^II ions has been demonstrated. The ligand was synthesised by a multi-steps by treating 5-amino-2-chlorobenzonitrile and cyclohexane -1,3-dione, the 5,5'-(((1E,3E)-cyclohexane-1,3-diylidene)bis(azanylylidene))bis(2-chlorobenzonitrile) was obtained. The precursor (M) was prepared  from the reaction 5,5'-(((1E,3E)-cyclohexane-1,3-diylidene)bis(azanylylidene))bis(2-chlorobenzonitrile) with NaN₃ to obtained (1E,3E)-N¹,N³-bis(4-chloro-3-(1H-tetrazol-5-yl)phenyl)cyclohexane-1,3-diimine (N). By reacting the precursor (M) with CS₂

<span lang="EN-US">The fundamental of a downlink massive multiple-input multiple-output (MIMO) energy- issue efficiency strategy is known as minimum mean squared error (MMSE) implementation degrades the performance of a downlink massive MIMO energy-efficiency scheme, so some improvements are adding for this precoding scheme to improve its workthat is called our proposal solution as a proposed improved MMSE precoder (PIMP). The energy efficiency (EE) study has also taken into mind drastically lowering radiated power while maintaining high throughput and minimizing interference issues. We further find the tradeoff between spectral efficiency (SE) and EE although they coincide at the beginning but later their interests become con

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.