High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction.

ZnIn2(Se1-xTex)4 (ZIST) chalcopyrite semiconductor thin films at various contents (x = 0.0, 0.2, and 0.4) are deposited on glass and p type silicon (111) substrate to produce heterojunction solar cell by using the thermal evaporation technique at RT where the thickness of 500 nm with a vacuum of 1×10-5 mbar and a deposited rates of 5.1 nm/s. This study focuses on how differing x content effect on the factors affecting the solar cell characteristics of ZIST thin film and n-ZIST/p-Si heterojunction. X-ray diffraction XRD investigation shows that this structure of ZIST film is polycrystalline and tetragonal, with (112) preferred orientation at 2θ ≈ 27.01. Moreover, atomic force microscopy AFM is studying the external morphology of