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IMPLEMENTATION OF ROOT FINDING ALGORITHM OF MINIMUM PHASE FILTER USING VHDL
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Root-finding is an oldest classical problem, which is still an important research topic, due to its impact on computational algebra and geometry. In communications systems, when the impulse response of the channel is minimum phase the state of equalization algorithm is reduced and the spectral efficiency will improved. To make the channel impulse response minimum phase the prefilter which is called minimum phase filter is used, the adaptation of the minimum phase filter need root finding algorithm. In this paper, the VHDL implementation of the root finding algorithm introduced by Clark and Hau is introduced.
VHDL program is used in the work, to find the roots of two channels and make them minimum phase, the obtained output results are similar in accuracy to the past work results, which is built by using MATLAB program. Using VHDL is necessary in FPGAs for building hardware of the root finding algorithm in lower cost and time. MATLAB program is used only for displaying the input and output discrete signals of tested channels.

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Publication Date
Tue Sep 23 2025
Journal Name
Journal Of Plant Protection Research
Smart sprayer for weed control using an object detection algorithm (yolov5)
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Spraying pesticides is one of the most common procedures that is conducted to control pests. However, excessive use of these chemicals inversely affects the surrounding environments including the soil, plants, animals, and the operator itself. Therefore, researchers have been encouraged to...

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Publication Date
Wed Apr 10 2019
Journal Name
Engineering, Technology & Applied Science Research
Content Based Image Clustering Technique Using Statistical Features and Genetic Algorithm
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Text based-image clustering (TBIC) is an insufficient approach for clustering related web images. It is a challenging task to abstract the visual features of images with the support of textual information in a database. In content-based image clustering (CBIC), image data are clustered on the foundation of specific features like texture, colors, boundaries, shapes. In this paper, an effective CBIC) technique is presented, which uses texture and statistical features of the images. The statistical features or moments of colors (mean, skewness, standard deviation, kurtosis, and variance) are extracted from the images. These features are collected in a one dimension array, and then genetic algorithm (GA) is applied for image clustering.

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Publication Date
Mon Nov 10 2025
Journal Name
2025 18th International Conference On Development In Esystem Engineering (dese)
Arrhythmia Recognition Algorithm Using Squared Krawtchouk-Tchebichef Polynomial-Based Feature Extraction
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Publication Date
Sat Jun 01 2019
Journal Name
Journal Of Engineering And Applied Sciences
Enhancing LSB algorithm against brute-force attack using ASCII mapping technique
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Publication Date
Fri Oct 03 2025
Journal Name
Mesopotamian Journal Of Computer Science
Enhanced TEA Algorithm Performance using Affine Transformation and Chaotic Arnold Map
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In digital images, protecting sensitive visual information against unauthorized access is considered a critical issue; robust encryption methods are the best solution to preserve such information. This paper introduces a model designed to enhance the performance of the Tiny Encryption Algorithm (TEA) in encrypting images. Two approaches have been suggested for the image cipher process as a preprocessing step before applying the Tiny Encryption Algorithm (TEA). The step mentioned earlier aims to de-correlate and weaken adjacent pixel values as a preparation process before the encryption process. The first approach suggests an Affine transformation for image encryption at two layers, utilizing two different key sets for each layer. Th

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Publication Date
Fri Jan 01 2016
Journal Name
Journal Of Computer And Communications
Pathfinding in Strategy Games and Maze Solving Using A* Search Algorithm
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Publication Date
Wed Jun 12 2013
Journal Name
International Journal Of Computer Applications
Design and Implementation of a Practical FTTH Network
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Fiber-to-the-Home (FTTH) has long been recognized as a technology that provides future proof bandwidth [1], but has generally been too expensive to implement on a wide scale. However, reductions in the cost of electro-optic components and improvements in the handling of fiber optics now make FTTH a cost effective solution in many situations. The transition to FTTH in the access network is also a benefit for both consumers and service providers because it opens up the near limitless capacity of the core long-haul network to the local user. In this paper individual passive optical components, transceivers, and fibers has been put together to form a complete FTTH network. Then the implementation of the under construction Baghdad/Al

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Publication Date
Fri Dec 29 2017
Journal Name
Al-khwarizmi Engineering Journal
Design and Implementation of a Proposal Network Firewall
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In today's world, most business, regardless of size, believe that access to Internet is imperative if they are going to complete effectively. Yet connecting a private computer (or a network) to the Internet can expose critical or confidential data to malicious attack from anywhere in the world since unprotected connections to the Internet (or any network topology) leaves the user computer vulnerable to hacker attacks and other Internet threats. Therefore, to provide high degree of protection to the network and network's user, Firewall need to be used.

Firewall provides a barrier between the user computer and the Internet (i.e. it prevents unauthor

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Publication Date
Tue Feb 28 2023
Journal Name
International Journal Of Intelligent Engineering And Systems
Design and Implementation of EEG-Based Smart Structure
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Publication Date
Fri Mar 01 2013
Journal Name
Journal Of Engineering
Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.