In this study, the harvest of maize silage with the cross double row sowing method were tested with a single row disc silage machine in two different PTO applications (540 and 540E min-1) and at two different working speeds v1, v2 (1.8 and 2.5 km h-1). The possibilities of harvesting with a single row machine were revealed, and performance characteristics such as hourly fuel consumption, field-product fuel consumption and PTO power consumption were determined in the trials. The best results in terms of hourly fuel consumption and PTO power consumption were determined in the 540E PTO application and V1 working speed. When the fuel consumption of the field-product is evaluated, it is obtained with V2 working speed and 540E PTO application. As

In this paper, an algorithm is suggested to train a single layer feedforward neural network to function as a heteroassociative memory. This algorithm enhances the ability of the memory to recall the stored patterns when partially described noisy inputs patterns are presented. The algorithm relies on adapting the standard delta rule by introducing new terms, first order term and second order term to it. Results show that the heteroassociative neural network trained with this algorithm perfectly recalls the desired stored pattern when 1.6% and 3.2% special partially described noisy inputs patterns are presented.

A comprehensive review focuses on 3D network-on-chip (NoC) simulators and plugins while paying attention to the 2D simulators as the baseline is presented. Discussions include the programming languages, installation configuration, platforms and operating systems for the respective simulators. In addition, the simulator’s properties and plugins for design metrics evaluations are addressed. This review is intended for the early career researchers starting in 3D NoC, offering selection guidelines on the right tools for the targeted NoC architecture, design, and requirements.

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets f