The presence of different noise sources and continuous increase in crosstalk in the deep submicrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achieves up to 25.3% power savings at 3-mm wire length as compared to the original nonadaptive scheme at the cost of only 3.4% power overhead in high protection mode.
When sites of new communication occurs which represents the merit of the development of communication technology which is characterized by the services of ( facebook-twiter-corapora-youtube-mass space-friendster-flicker-willnecked in addition to the direct services for viber-whatsup-telgram-and chat on) play important role in changing the infrastructure of Arabic societies which are consideredas closed and not changeable societies during near period and the significance of this study comes from the importounce of this subject which is considered as anew trend of the age on the field of media and public response and acceptance inspite of what is known about Arabic society-it doesn’t accept change-this occurance is associated with terms
... Show MoreIn this paper, the speed control of the real DC motor is experimentally investigated using nonlinear PID neural network controller. As a simple and fast tuning algorithm, two optimization techniques are used; trial and error method and particle swarm optimization PSO algorithm in order to tune the nonlinear PID neural controller's parameters and to find best speed response of the DC motor. To save time in the real system, a Matlab simulation package is used to carry out these algorithms to tune and find the best values of the nonlinear PID parameters. Then these parameters are used in the designed real time nonlinear PID controller system based on LabVIEW package. Simulation and experimental results are compared with each other and showe
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The process of accurate localization of the basic components of human faces (i.e., eyebrows, eyes, nose, mouth, etc.) from images is an important step in face processing techniques like face tracking, facial expression recognition or face recognition. However, it is a challenging task due to the variations in scale, orientation, pose, facial expressions, partial occlusions and lighting conditions. In the current paper, a scheme includes the method of three-hierarchal stages for facial components extraction is presented; it works regardless of illumination variance. Adaptive linear contrast enhancement methods like gamma correction and contrast stretching are used to simulate the variance in light condition among images. As testing material
... Show More<span>One of the main difficulties facing the certified documents documentary archiving system is checking the stamps system, but, that stamps may be contains complex background and surrounded by unwanted data. Therefore, the main objective of this paper is to isolate background and to remove noise that may be surrounded stamp. Our proposed method comprises of four phases, firstly, we apply k-means algorithm for clustering stamp image into a number of clusters and merged them using ISODATA algorithm. Secondly, we compute mean and standard deviation for each remaining cluster to isolate background cluster from stamp cluster. Thirdly, a region growing algorithm is applied to segment the image and then choosing the connected regi
... Show MoreA multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived that exhibit a regular arrangement of the cells (processors) and local interconnection pattern, which are important for VLSI implementation. It reduces latency time and increases the throughput rate in comparison to classical 1-D systolic arrays. The 3-D multilayered array consists of 2-D layers, which are connected with each other only by edges. Such arrays for LMS-based adaptive (FIR) filter may be opposed the fundamental requirements of fa
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