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Design & Implementation of High Switching & Low Phase Noise Frequency Synthesizer
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This research  describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc

  The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar &  reference divider in single chip. Therefore our system consists of  a single chip contains (low phase noise PFD, charge pump, prescalar  & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip is used to provide the following properties :

  • Low power consumption.
  • Small size, light weight.
  • Flexibility in selecting crystal oscillator frequencies to fit into the system frequency planning.
  • High reliability.

The application of this synthesizer  in frequency hopping systems, satellite communications & radar because it has high switching speed  ,low phase noise & low spurious level.

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Publication Date
Wed Aug 30 2023
Journal Name
Mathematical Modelling Of Engineering Problems
Dynamic Low Power Clustering Strategy in MWSN
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Publication Date
Wed Feb 09 2011
Journal Name
Journal Of Engineering
Low cost automatic sun path tracking system
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Solar tracking systems used are to increase the efficiency of the solar cells have attracted the attention of researchers recently due to the fact that the attention has been directed to the renewable energy sources. Solar tracking systems are of two types, Maximum Power Point Tracking (MPPT) and sun path tracking. Both types are studied briefly in this paper and a simple low cost sun path tracking system is designed using simple commercially available component. Measurements have been made for comparison between fixed and tracking system. The results have shown that the trackin

Publication Date
Sun Apr 30 2017
Journal Name
Journal Of Engineering
Implementation of a Proposed Load-Shedding System Using Altera DE2 FPGA
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A load-shedding controller suitable for small to medium size loads is designed and implemented based on preprogrammed priorities and power consumption for individual loads. The main controller decides if a particular load can be switched ON or not according to the amount of available power generation, load consumption and loads priorities. When themaximum allowed power consumption is reached and the user want to deliver power to additional load, the controller will decide if this particular load should be denied receiving power if its priority is low. Otherwise, it can be granted to receive power if its priority is high and in this case lower priority loads are automatically switched OFF in order not to overload the power generation. The

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Publication Date
Sat Dec 17 2022
Journal Name
Journal Of Al-ma'moon College
Simulation and Implementation of SNR Measurement processor for Adaptive Communication Systems
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Publication Date
Wed Jan 15 2020
Journal Name
Iraqi Journal Of Laser
Electronically Implementation and Detection of Pulse Laser from Continuous Laser Diode
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This research aims to design a high-speed laser diode driver and photodetector, the result is the
design of the high-speed laser diode driver with a short pulse of 10 ns at 30 KHz frequency and the
delivered maximum pulse voltage is 5.5 mV. Also, its optical output power of the laser diode driver is
about 2.529 mW for the centroied wavelength 1546.7 nm with FWHM of 286 pm and (1270-1610) nm.
The design of the circuit based on bipolar transistor where the input pulse signal is simply generated by
an arduino kit with 15 kHz frequency and then compensated to trigger to small signal amplifier which
was is simply NPN C3355 transistor and the output is a current driver to the laser diode. OptiSystem
software and Electronic

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Publication Date
Tue Jun 01 2021
Journal Name
Iop Conference Series: Earth And Environmental Science
Implementation of hierarchically porous zeolite-polymer membrane for Chromium ions removal
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Abstract<p>This work deals with the preparation of a zeolite/polymer flat sheet membrane with hierarchical porosity and ion-exchange properties. The performance of the prepared membrane was examined by the removal of chromium ions from simulated wastewater. A NaY zeolite (crystal size of 745.8 nm) was prepared by conventional hydrothermal treatment and fabricated with polyethersulfone (15% PES) in dimethylformamide (DMF) to obtain an ion-exchange ultrafiltration membrane. The permeate flux was enhanced by increasing the zeolite content within the membrane texture indicating increasing the hydrophilicity of the prepared membranes and constructing a hierarchically porous system. A membrane contain</p> ... Show More
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Publication Date
Sat Oct 01 2011
Journal Name
Journal Of Engineering
IMPLEMENTATION OF GYPSEOUS SOIL-ASPHALT STABILIZATION TECHNIQUE FOR BASE COURSE CONSTRUCTION
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The aim of this research work is to study the effect of stabilizing gypseous soil, which covers
vast areas in the middle, west and south parts of Iraq, using liquid asphalt on its strength properties
to be used as a base course layer replacing the traditional materials of coarse aggregate and broken
stones which are scarce at economical prices and hauling distances.
Gypseous soil brought from Al-Ramadi City, west of Iraq, with gypsum content of 66.65%,
medium curing cutback asphalt (MC-30), and hydrated lime are used in this study.
The conducted tests on untreated and treated gypseous soil with different percentages of medium
curing cutback asphalt (MC-30), water, and lime were: unconfined compression strength, and o

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Publication Date
Sun Feb 10 2019
Journal Name
Journal Of The College Of Education For Women
IMPLEMENTATION OF THE SKIP LIST DATA STRUCTURE WITH IT'S UPDATE OPERATIONS
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A skip list data structure is really just a simulation of a binary search tree. Skip lists algorithm are simpler, faster and use less space. this data structure conceptually uses parallel sorted linked lists. Searching in a skip list is more difficult than searching in a regular sorted linked list. Because a skip list is a two dimensional data structure, it is implemented using a two dimensional network of nodes with four pointers. the implementation of the search, insert and delete operation taking a time of upto . The skip list could be modified to implement the order statistic operations of RANKand SEARCH BY RANK while maintaining the same expected time. Keywords:skip list , parallel linked list , randomized algorithm , rank.

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Publication Date
Sat Apr 01 2023
Journal Name
Bulletin Of Electrical Engineering And Informatics
Implementation and performance evaluation of multi level pseudo random sequence generator
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In this paper, introduce a proposed multi-level pseudo-random sequence generator (MLPN). Characterized by its flexibility in changing generated pseudo noise (PN) sequence according to a key between transmitter and receiver. Also, introduce derive of the mathematical model for the MLPN generator. This method is called multi-level because it uses more than PN sequence arranged as levels to generation the pseudo-random sequence. This work introduces a graphical method describe the data processing through MLPN generation. This MLPN sequence can be changed according to changing the key between transmitter and receiver. The MLPN provides different pseudo-random sequence lengths. This work provides the ability to implement MLPN practically

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Publication Date
Tue Jan 01 2013
Journal Name
Communications And Network
Link and Cost Optimization of FTTH Network Implementation through GPON Technology
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