Here, a high sensitive method for biomarker identification according to nanostructure, using enzyme-linked immunosorbent assays (ELISAs), called Nano-ELISA, was presented. Different shapes of gold nanostructures (star and sphere; GNSs and GNPs) with a particle size of 40 nm for sphere particles were altered with a monoclonal antibody (Ab) as a detector Ab. To amplify the optical signal, gold nanostructures were employed as carriers of the signaling specific antibody against insulin growth factor binding protein- 3 (IGFBP-3). The substrate was catalytically oxidized by the Horseradish Peroxidase (HRP) conjugated gold nanostructure, and HRP also enhanced the optical signals, reflecting the amount of the targeting IGFBP-3. In comparison to the classical ELISA procedure, this assay using gold nanostructure as an enhancer, have higher sensitivity and shorter testing time, in the spectrum between 0.05 ng/mL and 30 ng/mL. Gold nanostar based ELISA assay (GNS-based ELISA) have lower LOD, signal amplification potency, and higher specificity and sensitivity, compared to gold nanoparticles based ELISA (GNP- based ELISA) assay.
In the geotechnical and terramechanical engineering applications, precise understandings are yet to be established on the off-road structures interacting with complex soil profiles. Several theoretical and experimental approaches have been used to measure the ultimate bearing capacity of the layered soil, but with a significant level of differences depending on the failure mechanisms assumed. Furthermore, local displacement fields in layered soils are not yet studied well. Here, the bearing capacity of a dense sand layer overlying loose sand beneath a rigid beam is studied under the plain-strain condition. The study employs using digital particle image velocimetry (DPIV) and finite element method (FEM) simulations. In the FEM, an experiment
... Show MoreIt is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.