It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.

Reverse Osmosis (RO) has already proved its worth as an efficient treatment method in chemical and environmental engineering applications. Various successful RO attempts for the rejection of organic and highly toxic pollutants from wastewater can be found in the literature over the last decade. Dimethylphenol is classified as a high-toxic organic compound found ubiquitously in wastewater. It poses a real threat to humans and the environment even at low concentration. In this paper, a model based framework was developed for the simulation and optimisation of RO process for the removal of dimethylphenol from wastewater. We incorporated our earlier developed and validated process model into the Species Conserving Genetic Algorithm (SCG

Wireless Body Area Network (WBAN) is a tool that improves real-time patient health observation in hospitals, asylums, especially at home. WBAN has grown popularity in recent years due to its critical role and vast range of medical applications. Due to the sensitive nature of the patient information being transmitted through the WBAN network, security is of paramount importance. To guarantee the safe movement of data between sensor nodes and various WBAN networks, a high level of security is required in a WBAN network. This research introduces a novel technique named Integrated Grasshopper Optimization Algorithm with Artificial Neural Network (IGO-ANN) for distinguishing between trusted nodes in WBAN networks by means of a classifica

The issue of increasing the range covered by a wireless sensor network with restricted sensors is addressed utilizing improved CS employing the PSO algorithm and opposition-based learning (ICS-PSO-OBL). At first, the iteration is carried out by updating the old solution dimension by dimension to achieve independent updating across the dimensions in the high-dimensional optimization problem. The PSO operator is then incorporated to lessen the preference random walk stage's imbalance between exploration and exploitation ability. Exceptional individuals are selected from the population using OBL to boost the chance of finding the optimal solution based on the fitness value. The ICS-PSO-OBL is used to maximize coverage in WSN by converting r

The gas-lift method is crucial for maintaining oil production, particularly from an established field when the natural energy of the reservoirs is depleted. To maximize oil production, a major field's gas injection rate must be distributed as efficiently as possible across its gas-lift network system. Common gas-lift optimization techniques may lose their effectiveness and become unable to replicate the gas-lift optimum in a large network system due to problems with multi-objective, multi-constrained & restricted gas injection rate distribution. The main objective of the research is to determine the possibility of using the genetic algorithm (GA) technique to achieve the optimum distribution for the continuous gas-lift injectio

Some degree of noise is always present in any electronic device that
transmits or receives a signal . For televisions, this signal i has been to s the
broadcast data transmitted over cable-or received at the antenna; for digital
cameras, the signal is the light which hits the camera sensor. At any case, noise
is unavoidable. In this paper, an electronic noise has been generate on
TV-satellite images by using variable resistors connected to the transmitting cable
. The contrast of edges has been determined. This method has been applied by
capturing images from TV-satellite images (Al-arabiya channel) channel with
different resistors. The results show that when increasing resistance always
produced higher noise f

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.