Software Defined Networking (SDN) with centralized control provides a global view and achieves efficient network resources management. However, using centralized controllers has several limitations related to scalability and performance, especially with the exponential growth of 5G communication. This paper proposes a novel traffic scheduling algorithm to avoid congestion in the control plane. The Packet-In messages received from different 5G devices are classified into two classes: critical and non-critical 5G communication by adopting Dual-Spike Neural Networks (DSNN) classifier and implementing it on a Virtualized Network Function (VNF). Dual spikes identify each class to increase the reliability of the classification
... Show MoreSoftware Defined Networking (SDN) with centralized control provides a global view and achieves efficient network resources management. However, using centralized controllers has several limitations related to scalability and performance, especially with the exponential growth of 5G communication. This paper proposes a novel traffic scheduling algorithm to avoid congestion in the control plane. The Packet-In messages received from different 5G devices are classified into two classes: critical and non-critical 5G communication by adopting Dual-Spike Neural Networks (DSNN) classifier and implementing it on a Virtualized Network Function (VNF). Dual spikes identify each class to increase the reliability of the classification. Different
... Show MoreIt is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.
Modern statistical techniques offer a range of methodologies for modelling time series data, with conditional and unconditional approaches providing complementary insights that enhance overall model accuracy. This article introduced a modified ARIMA model employing conditional and unconditional parameter estimates. The methodology for the new model based on novel methods is provided. The prediction process, one and two steps ahead, is covered in detail, and a novel algorithm is presented. The best model is picked based on various measurement criteria, such as coefficient of determination (R2), root mean squared error (RMSE), and mean absolute scaled error (MASE). The suggested model is applied to a monthly petrol sales dataset (Jan
... Show MoreIn this paper a system is designed and implemented using a Field Programmable Gate Array (FPGA) to move objects from a pick up location to a delivery location. This transportation of objects is done via a vehicle equipped with a robot arm and an FPGA. The path between the two locations is followed by recognizing a black line between them. The black line is sensed by Infrared sensors (IR) located on the front and on the back of the vehicle. The Robot was successfully implemented by programming the Field Programmable Gate Array with the designed system that was described as a state diagram and the robot operated properly.
In this study, from a total of 856 mastitis cases in lactating ewes, only 34 Streptococcus agalactiae isolates showed various types of resistance to three types of antibiotics (Penicillin, Erythromycin and Tetracycline). St. agalactiae isolates were identified according to the standard methods, including a new suggested technique called specific Chromogenic agar. It was found that antibiotic bacterial resistance was clearly identified by using MIC-microplate assay (dilution method). Also, by real-time PCR technique, it was determined that there were three antibiotics genes resistance ( pbp2b, tetO and mefA ). The high percentage of isolate carried of a single gene which was the Tetracycline (20.59%) followed by percentage Penicillin was
... Show MoreIn every country in the world, there are a number of amputees who have been exposed to some accidents that led to the loss of their upper limbs. The aim of this study is to suggest a system for real-time classification of five classes of shoulder girdle motions for high-level upper limb amputees using a pattern recognition system. In the suggested system, the wavelet transform was utilized for feature extraction, and the extreme learning machine was used as a classifier. The system was tested on four intact-limbed subjects and one amputee, with eight channels involving five electromyography channels and three-axis accelerometer sensor. The study shows that the suggested pattern recognition system has the ability to classify the sho
... Show MoreThis research has come out with that strategies made by Porter as generally strategies applicable to any size and type of economic units cannot be applied to many of the economic units in the world in generally and in Iraq especially not a lot of economic units have the resources and competencies that enable them to provide a unique product of its kind in the minds of customers and then adopt a differentiation strategy and not a lot of economic units have the resources and competencies that make them the cost leader. Differentiators and cost leaders are minority in the world while not differentiators and not cost leaders are majority in the world.
The economic units are not differentiators and not c
... Show MoreIt is important that real time stability in smart grids is ensured as the integration of renewables and the complexity of the systems grows. In this paper, we provide a solid architecture, which combines a Residual CNNLSTM deep neural network predictor, FPGA-accelerated Model Predictive Control (MPC), and SHAP-based explainability. The proposed method predicted with 99.8% accuracy using the Electrical grid Stability Simulated Dataset (UCI) and minimized the instability rates surpassing 85 percent in all operating conditions. Meeting real-time operating needs, FPGA deployment on a Xilinx Zynq UltraScale+ provided 3.1 ms latency and 5 times reduced energy consumption against CPU processing. By emphasizing bus voltage and frequency as major in
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