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Design and Implementation of an Intelligent Electronic Circuit to Control Laser Power in Real Time Using Built-In Thermal Feedback
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Publication Date
Sun Jan 01 2023
Journal Name
Journal Of Engineering
Intelligent Congestion Control of 5G Traffic in SDN using Dual-Spike Neural Network
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Software Defined Networking (SDN) with centralized control provides a global view and achieves efficient network resources management. However, using centralized controllers has several limitations related to scalability and performance, especially with the exponential growth of 5G communication. This paper proposes a novel traffic scheduling algorithm to avoid congestion in the control plane. The Packet-In messages received from different 5G devices are classified into two classes: critical and non-critical 5G communication by adopting Dual-Spike Neural Networks (DSNN) classifier and implementing it on a Virtualized Network Function (VNF). Dual spikes identify each class to increase the reliability of the classification

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Scopus (9)
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Publication Date
Sun Jan 01 2023
Journal Name
Journal Of Engineering
Intelligent Congestion Control of 5G Traffic in SDN using Dual-Spike Neural Network
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Software Defined Networking (SDN) with centralized control provides a global view and achieves efficient network resources management. However, using centralized controllers has several limitations related to scalability and performance, especially with the exponential growth of 5G communication. This paper proposes a novel traffic scheduling algorithm to avoid congestion in the control plane. The Packet-In messages received from different 5G devices are classified into two classes: critical and non-critical 5G communication by adopting Dual-Spike Neural Networks (DSNN) classifier and implementing it on a Virtualized Network Function (VNF). Dual spikes identify each class to increase the reliability of the classification. Different

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Scopus (9)
Crossref (6)
Scopus Crossref
Publication Date
Thu May 18 2023
Journal Name
Journal Of Engineering
Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.

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Publication Date
Mon Mar 30 2026
Journal Name
Iraqi Journal Of Science
A modified time series model using conditional and unconditional estimations with applications to a real dataset
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Modern statistical techniques offer a range of methodologies for modelling time series data, with conditional and unconditional approaches providing complementary insights that enhance overall model accuracy. This article introduced a modified ARIMA model employing conditional and unconditional parameter estimates. The methodology for the new model based on novel methods is provided. The prediction process, one and two steps ahead, is covered in detail, and a novel algorithm is presented. The best model is picked based on various measurement criteria, such as coefficient of determination (R2), root mean squared error (RMSE), and mean absolute scaled error (MASE). The suggested model is applied to a monthly petrol sales dataset (Jan

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Publication Date
Mon Mar 08 2021
Journal Name
Journal Of Physics: Conference Series
Design and Implementation of a Moving Robot Equipped with an Arm and an FPGA to Deliver Objects between Two Positions
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Abstract<p>In this paper a system is designed and implemented using a Field Programmable Gate Array (FPGA) to move objects from a pick up location to a delivery location. This transportation of objects is done via a vehicle equipped with a robot arm and an FPGA. The path between the two locations is followed by recognizing a black line between them. The black line is sensed by Infrared sensors (IR) located on the front and on the back of the vehicle. The Robot was successfully implemented by programming the Field Programmable Gate Array with the designed system that was described as a state diagram and the robot operated properly.</p>
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Publication Date
Tue Sep 08 2020
Journal Name
Baghdad Science Journal
Using Real-Time PCR to Investigate Some of Antibiotic Resistance Genes from Streptococcus agalactiae Isolates from ewe Mastitis cases in Nineveh province
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In this study, from a total of 856 mastitis cases in lactating ewes, only 34 Streptococcus agalactiae isolates showed various types of resistance to three types of antibiotics (Penicillin, Erythromycin and Tetracycline). St. agalactiae isolates were identified according to the standard methods, including a new suggested technique called specific Chromogenic agar. It was found that antibiotic bacterial resistance was clearly identified by using MIC-microplate assay (dilution method). Also, by real-time PCR technique, it was determined that there were three antibiotics genes resistance ( pbp2b, tetO and mefA ). The high percentage of isolate carried of a single gene which was the Tetracycline (20.59%) followed by percentage Penicillin was

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Publication Date
Thu May 23 2019
Journal Name
The International Journal Of Artificial Organs
Real-time classification of shoulder girdle motions for multifunctional prosthetic hand control: A preliminary study
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In every country in the world, there are a number of amputees who have been exposed to some accidents that led to the loss of their upper limbs. The aim of this study is to suggest a system for real-time classification of five classes of shoulder girdle motions for high-level upper limb amputees using a pattern recognition system. In the suggested system, the wavelet transform was utilized for feature extraction, and the extreme learning machine was used as a classifier. The system was tested on four intact-limbed subjects and one amputee, with eight channels involving five electromyography channels and three-axis accelerometer sensor. The study shows that the suggested pattern recognition system has the ability to classify the sho

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Scopus (5)
Crossref (5)
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Publication Date
Tue Jul 01 2025
Journal Name
Mastering The Minds Of Machines
Deep Reinforcement Learning: Bridging Learning and Control in Intelligent Systems
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Publication Date
Sat Sep 01 2012
Journal Name
Journal Of Economics And Administrative Sciences
Using Target Costing in Implementation Confrontational Strategy Applied study in General Company for Electronic Industries
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This research has come out with that strategies made by Porter as generally strategies applicable to any size and type of economic units cannot be applied to many of the economic units in the world in generally and in Iraq especially not a lot of economic units have the resources and competencies that enable them to provide a unique product of its kind in the minds of customers and then adopt a differentiation strategy  and not a lot of economic units have the resources and competencies that make them the cost leader. Differentiators and cost leaders are minority in the world while not differentiators and not cost leaders are majority in the world.

The economic units are not differentiators and not c

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Crossref
Publication Date
Tue Dec 16 2025
Journal Name
Radioelectronics. Nanosystems. Information Technologies.
Intelligent Control and Stability Analysis of Smart Grids Using CNN-LSTM Network and Model Predictive Controller
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It is important that real time stability in smart grids is ensured as the integration of renewables and the complexity of the systems grows. In this paper, we provide a solid architecture, which combines a Residual CNNLSTM deep neural network predictor, FPGA-accelerated Model Predictive Control (MPC), and SHAP-based explainability. The proposed method predicted with 99.8% accuracy using the Electrical grid Stability Simulated Dataset (UCI) and minimized the instability rates surpassing 85 percent in all operating conditions. Meeting real-time operating needs, FPGA deployment on a Xilinx Zynq UltraScale+ provided 3.1 ms latency and 5 times reduced energy consumption against CPU processing. By emphasizing bus voltage and frequency as major in

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