In the geotechnical and terramechanical engineering applications, precise understandings are yet to be established on the off-road structures interacting with complex soil profiles. Several theoretical and experimental approaches have been used to measure the ultimate bearing capacity of the layered soil, but with a significant level of differences depending on the failure mechanisms assumed. Furthermore, local displacement fields in layered soils are not yet studied well. Here, the bearing capacity of a dense sand layer overlying loose sand beneath a rigid beam is studied under the plain-strain condition. The study employs using digital particle image velocimetry (DPIV) and finite element method (FEM) simulations. In the FEM, an experiment

Aqueous Two Phase System (ATPS) or liquid-liquid extraction is used in biotechnology to recover valuable compounds from raw sources. In Aqueous Two-Phase Systems, many factors influence the Partition coefficient, K, (which is the ratio of protein concentration in the top phase to that in the bottom phase) and the Recovery percentage (Rec%). In this research, two systems of ATPS were used: first, polyethylene glycol (PEG) 4000/Sodium citrate (SC), and the second, PEG8000/ Sodium phosphate (SPH), for the extraction of Bovine Serum Albumin (BSA). The behavior of Rec% and K of pure (BSA) in ATPS has been investigated throughout the study by the effects of five parameters: temperature, concentration of polyethylene glycol (P

<span lang="EN-US">The fundamental of a downlink massive multiple-input multiple-output (MIMO) energy- issue efficiency strategy is known as minimum mean squared error (MMSE) implementation degrades the performance of a downlink massive MIMO energy-efficiency scheme, so some improvements are adding for this precoding scheme to improve its workthat is called our proposal solution as a proposed improved MMSE precoder (PIMP). The energy efficiency (EE) study has also taken into mind drastically lowering radiated power while maintaining high throughput and minimizing interference issues. We further find the tradeoff between spectral efficiency (SE) and EE although they coincide at the beginning but later their interests become con

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.